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Patent No.
3,821,715
(filed January 1973, granted June 28, 1974)
The patent covers only the external bus organization and the memory addressing scheme of the Intel MCS-4
chip set. The patent does not cover the internal architecture of the 4004 microprocessor chip, nor its design or manufacturing methods. The naming order (Hoff, Mazor, Faggin) of this rather limited patent does not imply the order of contribution to the actual creation of the world’s first microprocessor, as it is generally assumed, but rather the order of contribution to the specific claims of the patent. This patent acquired its value, post factum, primarily because the 4004 was actually implemented, independently and outside the scope of the patent’s teachings. See also Gilbert Gilbert Hyatt patent.
Specifically, the patent claims the particular method of addressing the ROM (4001) and the RAM (4002) chips so that only the selected chip can communicate with the common 4-bit, bi-directional data bus. It also claims the use of dynamic RAM memory with on-board means of memory refresh, the use of a timing synchronization signal sent by the CPU chip to all the other chips, and the inclusion of input and output ports in the memory chips. The latter claims are conditional to the chips being connected with the 4-bit, bi-directional data bus described in the first claim. This patent was useful primarily in protecting Intel from unauthorized copying of the chip set.
It is a curious fact that the specific bus organization of the MCS-4, the main subject of this patent, was responsible for substantially reducing the throughput of the system that would otherwise have been possible with the silicon gate technology. It was dictated by Les Vadasz and Andy Grove’s imposition to use only 16-pin packages for all the chips. By using separate lines for address and data, instead of a time multiplexed 4-bit bus, it would have been possible to create a 4004 with an instruction cycle time of 4 microseconds (3 clock cycles) instead of the actual 10.7 microseconds (using 8 clock cycles). It is only because of the superiority of the silicon gate technology over metal gate technology that the MCS-4 performance was still better than the performance of the Rockwell PPS-4, a competing 4-bit chip set made with metal gate MOS technology. Introduced in the summer of 1972, the PPS-4 used a dynamic 4-phase design technique, the most effective design methodology of the day for random logic with metal gate, and all the chips were packaged in 42-pin packages. The PPS-4 CPU could fetch and execute an instruction in 3 clock cycles, since it used separate lines for address and data. With a maximum clock frequency of 200kHz (versus the 750 kHz of the MCS-4), the PPS-4 instruction cycle was 15 microseconds (versus the 10.7 microseconds of the MCS-4). | |
Patent No.
3,753,011
(filed March 13, 1972, granted August 14, 1973)
This patent covers a special
circuit invented by Faggin and used in the 4004 that
allowed to reset the CPU when power was first turned on.
This circuit eliminated the requirement of an extra pin
(the 4004 had only 16 pins) and the requirement of an
external circuit to reset the chip. The same circuit was
also used in the other members of the 4000
family. | |
