Silicon Gate Technology
The Intel 4004 Microprocessor and the Silicon Gate Technology
A testimonial from Federico Faggin, designer of the 4004 and developer of its enabling technology
The Silicon Gate Technology
The Silicon Gate Technology was the world’s first commercial MOS self-aligned-gate process technology. Before this technology, the control gate of the MOS transistor was made with aluminum instead of polycrystalline silicon. Aluminum-gate MOS transistors were three to four times slower, consumed twice as much silicon area, had higher leakage current and lower reliability compared with silicon-gate transistors. Faggin created the silicon gate technology in 1968 while working in the R&D Laboratories of Fairchild Semiconductor in Palo Alto, CA. He also designed and built the world's first commercial integrated circuit using the silicon gate technology: the Fairchild 3708 - an 8-bit analog multiplexer with decoding logic. The first 3708 was fabricated in July 1968 and demonstrated a substantially improved performance over its metal-gate counterpart (called the 3705) and became commercially available in October 1968.

In 1968, almost all the integrated circuits sold used bipolar transistors. Bipolar transistors were about 100 times faster than MOS transistors but consumed much more power, required more silicon area, and used a much more complicated and costly manufacturing process. MOS technology was considered by most practitioners of the time promising but inadequate, with little chance of supplanting the bipolar technology. With the advent of the silicon gate technology, however, MOS technology, in less than 10 years, replaced bipolar technology as the vehicle of choice for complex integrated circuits.

While at Intel, Faggin fostered the use of a new manufacturing process called "depletion load" and, in 1974, supervised Richard Pashley, just hired at Intel, in the design of the first 1024-bit, N-channel, 5-Volt, static RAM with less than 100 nsec access time, bringing the performance of MOS memory chips close to the speed of bipolar RAMs. That was the beginning of the end for bipolar technology, by then only entrenched in the fast, static RAM business. Within a few more years, most of the integrated circuits sold were made using silicon gate technology.

History of the self-aligned MOS process technology
The first step leading to self-aligned gate integrated circuits, started with the work of Robert W. Bower who in 1966 proposed a method for the reduction of the parasitic capacitances of an MOS transistor, whereby the gate electrode itself was used as a mask to define the source and drain regions of the transistor. Dr. Bower proposed to use the aluminum gate – aluminum was the material the gate was made of in those days -- to shield against the ion implantation of the dopant necessary to form the source and drain junctions. In 1966, ion implantation was a new doping technique still in development at Hughes Aircraft, the employer of Dr. Bower, and not yet available at other labs.

While conceptually the idea was sound, in practice it didn’t work -- no commercial IC was ever produced with Bower’s method -- since it was impossible to adequately passivate the transistors and also impossible to repair the radiation damage done to the silicon crystal structure by the ion implantation (this is normally done by thermal annealing). Both steps required temperatures far in excess of the temperatures survivable by the aluminum gate. A more refractory material was needed.

In 1967 John C. Sarace and collaborators at Bell Labs replaced the aluminum gate with an electrode made of vacuum-evaporated amorphous silicon and succeeded in building working self-aligned gate MOS transistors. The process, however, was suitable only for the fabrication of discrete transistors and not for integrated circuits and was never pursued beyond the proof of principle.

In early 1968, following some exploratory work done by Tom Klein, Faggin extended the Bell Labs idea of an MOS gate made of amorphous silicon to create a new manufacturing process that could produce reliable, commercial, self-aligned-gate MOS integrated circuits (IC). By April 1968, Faggin made the first working test structures using his new method and by July 1968 he completed the design and fabrication of the first fully functional integrated circuit to use self-aligned gate MOS transistors – the Fairchild 3708, an 8-bit analog multiplexer with decoding logic. The first fully functional 3708 samples were shipped to customers in October 1968 and, soon after that time, the device became commercially available to the general market.

A number of innovations were necessary to make this process possible:

1. A novel process architecture (the sequence of masking steps and their topology.)

2. Replacing vacuum-evaporated amorphous silicon with poly-crystalline silicon obtained by vapor phase deposition, since evaporated, amorphous silicon did break at oxide steps. In the Bell Labs experiments, the amorphous silicon did not go over oxide steps; this is the reason why only discrete transistors could be fabricated and the process was unsuitable for integrated circuits.

3. A reliable method for etching the polysilicon material,

4. The use of phosphorous gettering to soak up the impurities, always present in the transistor, causing reliability problems.

The SGT was also adopted by Intel at its founding (1968), and within a few years became the core technology for the fabrication of MOS integrated circuits worldwide, lasting to this day.

In-Depth Analysis of MOS Silicon Gate Technology Benefits
Comparing conventional aluminum gate MOS integrated circuits with similar circuits fabricated with the self-aligned SGT, the following benefits are noted:

1. Fast and low power consuming. The major contribution to the superior speed of SGT ICs was due to the drastic reduction of the overlap capacitances between the gate electrode and the source and drain junctions. The gate to drain overlap capacitance has the most impact on speed because it appears at the input multiplied by the gain of the circuit (the so-called Miller effect.) In conventional aluminum gate MOS transistors, the need for registration tolerances not only increases the overlap capacitances, substantially reducing the nominal speed, but also dramatically increases the speed variability from wafer to wafer due to differences in alignment. An additional speed advantage of P-channel, MOS integrated circuits fabricated on [100] silicon wafers was the reduction of the threshold voltage by 1.1 Volt (approximately 30%) compared with similar transistors made with aluminum gate on the same crystal-orientation silicon (Most MOS ICs made in 1968 used [111] orientation and had much higher threshold voltages than devices built with [100] orientaion). The threshold voltage reduction was due to the fact that the work function difference between the heavily P-doped polysilicon gate and the N-doped silicon substrate is 1.1 volt lower than the work function difference between the aluminum gate and the same silicon substrate. Lower threshold voltage allowed the use of a lower supply voltage, which in turn made possible faster, less power consuming and more reliable circuits. Increased reliability was a direct consequence of the reduced height of oxide steps due to the lower supply voltage requirement (thinner field oxide could be made because the field parasitic MOS threshold voltage could be lowered). The bottom line was that, for the same power dissipation, SGT circuits were faster by a factor of 3 to 5 times over conventional MOS circuits. Alternatively, for the same speed, the power dissipation could be reduced by a factor of 3 to 5 times over conventional MOS ICs.

2. Cost-effective. In aluminum-gate MOS ICs the circuit area was primarily determined by the metal layer. SGT ICs, however, used approximately half the silicon area used by conventional MOS ICs to perform the same function. Most of the density increase was due to the use of polysilicon not only for the gates of transistors, but also for the interconnections. Since the aluminum layer could overlap the polysilicon layer, the entire transistor structure could be compacted and polysilicon provided an additional layer of interconnections. Since cost is proportional to the chip area (assuming that the wafer cost is approximately the same for the two processes, which was the case with SGT,) the SGT die cost could also be reduced to about half that of a conventional MOS IC performing the same function. Smaller die contributed also to an additional speed improvement since interconnection parasitic capacitances could be further reduced. Faggin also invented the “buried contact” at Fairchild: a method for making direct connections between the polysilicon and junctions, without the use of aluminum. This method provided the equivalent of two full layers of interconnections and was indispensable to the fabrication of the 4004.

3. Reliable. Conventional MOS devices, in 1968, had poor reliability due to two primary causes: threshold voltage drift due to impurities present in silicon dioxide, aluminum and silicon; and aluminum breakage over oxide steps. The SGT improved device reliability due to both causes: Impurities could be greatly reduced by the use of phosphorous gettering. Gettering was done after the transistors were completely formed and sealed, but before the deposition of aluminum (with SGT, aluminum is only used for interconnections and is not part of the active transistor, like is the case for metal gate MOS). Since gettering uses temperatures that aluminum cannot withstand, it could not be used in aluminum-gate MOS transistors. The breakage of the silicon gate was eliminated by the use of vapor-phase deposition of polysilicon, instead of vacuum evaporation of amorphous silicon. The phosphorous gettering process was also used to smooth out the oxide steps, eliminating the breakage of aluminum. Reliability was increased to the level of conventional bipolar integrated circuits, then the dominant IC technology, eliminating the major obstacle to broad adoption of MOS technology. Phosphorous gettering did also drastically reduce the junction leakage current allowing dynamic circuits to store charge for far longer time periods than conventional MOS technology could – a critical advantage in the fabrication of dynamic memories.

4. New functions. With SGT, new device types, not possible with conventional technology, could be fabricated. In particular, charge coupled devices (CCD), used for image sensors, and non-volatile memory devices using floating silicon-gate structures (silicon gates not connected to anything), such as flash memories and EEPROM devices. These devices dramatically enlarged the range of functions that could be made with solid state electronics.

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