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The New Methodology for Random Logic Design Used in the 4004 and in All the Early Intel Microprocessors: The Silicon Gate Design Methodology
By April 1970, when Federico Faggin started the design of the MCS-4 chip set at Intel, only a few silicon gate chips had been designed and commercially introduced in the market. The first was the Fairchild 3708, an 8-channel analog multiplexer with decoding logic, designed by Faggin in 1968. This was followed by the Intel 1101, a 256-bit static memory, plus a family of dynamic shift registers designed by L. Vadasz and J. Karp in 1969.
In 1970 there were three major classes of MOS integrated circuits: 1) Mask-programmable ROM chips; 2) Shift registers, which were the primary form of read-write memory commercially available; and 3) Custom random logic devices, like the MCS-4 was originally intended to be. The microprocessor – one of the four chips of the MCS-4 family – became the world's first general purpose random logic chip ever designed.
The 4004 was mostly a random logic circuit, a type of integrated circuit where there are many circuit blocks, each different from the others. This is in contrast with memory circuits which use only a few circuit blocks repeated over and over again. At Intel -- a memory company -- there was no expertise and no infrastructure for random logic design. Furthermore, the Silicon Gate Techonology (SGT) required a different design and a novel layout strategy than aluminum-gate MOS for random logic circuits.
The practice of the day for the design of custom MOS random logic chips at suppliers such as American Microsystems (AMI), General Instruments, Texas Instruments and Fairchild Semiconductor, was to use computer-assisted circuit design and layout using a family of circuit building blocks (cells) that had been previously designed, laid-out and characterized. The starting point was a verified logic diagram made by the customer. The MOS vendor would then convert the customer logic design into a circuit design, utilizing the pre-characterized building blocks, thus generating the guiding document for the layout of each chip. Custom MOS vendors had a fairly large collection of circuit blocks, together with cell-selection and placement rules, and standardized design methods. They also had logic and circuit simulation programs, as well as hardware and software tools for the generation of test programs used for debugging and testing of the chips. And finally, they also
had a library of developed chips that provided very helpful implementation examples.
Using metal-gate MOS technology, there were three major types of random logic design styles: 1) Fully static asynchronous design, capable of performing down to DC level; 2) Two-phase synchronous logic, which was a mixture of static and dynamic circuitry; and 3) Four-phase, fully dynamic, synchronous logic design.
Of the three techniques, fully static design required the largest number of transistors and had the worse speed-power product. Four-phase design achieved the best speed-power product and a circuit density similar to two-phase design, but required a high level of computer assisted design that Intel did not possess. To Federico's knowledge, only Rockwell International and Four-Phase Systems had the expertise to design complex four-phase chips at that time.
Since the 4004 was the first complex random logic circuit designed with SGT, its design required the creation of a new design methodology that didn't exist, either at Fairchild or at Intel, the only two companies that had the MOS silicon gate process. Federico Faggin, its inventor and developer, calls it Silicon Gate Design Methodology (SGDM).
Two-phase design was the only available alternative given the speed and power dissipation needed, combined with the 4004 complexity. However, two-phase logic required the use of bootstrap loads to achieve the needed speed-power product. Everybody at Intel and Fairchild believed that bootstrap load could not be manufactured with SGT, unless an additional masking layer was used. In fact, at Fairchild, design engineers had been resisting the use of the SGT because they couldn’t make bootstrap load devices. They also believed that there was no area advantage to SGT when compared with metal-gate, despite Faggin’s claims to the contrary. When he addressed this complaint, he found that the reason why SGT was found lacking was because the design engineers were mindlessly translating with SGT the old aluminum-gate circuit topologies, without the necessary rethinking. SGT was different enough that
many old practices didn’t work well anymore, and new tricks were required.
Moreover, to achieve the necessary circuit density for the 4004 to be manufacturable with good yields, it was necessary to use the buried contact, a process technique Faggin had invented at Fairchild in 1968. This technique needed one additional masking layer to allow the direct connection of poly-silicon lines to junctions under oxide. By eliminating the otherwise required metal bridge, two layers of interconnections became available, dramatically reducing the area of random logic circuits.
A few months before leaving Fairchild to join Intel, Faggin also figured out and tested a way to make bootstrap-load devices, eliminating all limitations to the use of the SGT for the design of power-efficient and fast two-phase random logic circuits.
When he joined Intel, Faggin found that the company not only had no expertise and no infrastructure for the design of random logic circuits, but also that the MCS-4 project was behind schedule by six months, therefore he had to devise fast ways to design the four MCS-4 chips. His first task was to create the basic rules for the worst-case design of the various gates and flip-flops needed. He was familiar with worst-case design techniques, having used them with discrete bipolar transistor logic families, therefore he adapted his knowledge to the situation at hand by doing worst-case design of MOS gates, based on realistic noise margins, and using graphic design (the same techniques he had learned at school for the design of vacuum tubes circuits), based on the normalized measured characteristics of MOS transistors fabricated at Intel.
The intimate knowledge of the SGT process technology that Faggin had earned by developing it at Fairchild Semiconductor in 1968, together with his experience of computer architecture, logic and circuit design gave him a unique vantage point to create the new SGDM, a flexible methodology with the best balance between the various factors that needed to be traded off (speed, power dissipation and chip area).
The SGDM started with minimizing the number of translations necessary to design the MCS-4 chips, enabling the most effective design possible, i.e. the highest speed for the allowed power dissipation, with the smallest possible chip area, while minimizing the possibility of making costly mistakes. This new method is explained below, after a brief description of the design methods in general use at the time.
In 1970, the typical design flow started with the completion of the overall chip specifications. The specifications were followed by the logic design, then by the circuit design, and finally by the chip layout. The logic design and the overall chip specifications were typically done by the customer. Going from one step to the next, required a translation from the language of logic gates with their symbols, to the language of circuits made with individual transistors, and using different symbols, to the geometrical patterns of the layout, representing the physical implementation of the transistors and their interconnections. People with different skills were normally used at each step, therefore the synergy between the different phases of the design often was not fully realized.
The SGDM made it possible to go directly from the chip specification to a single design document that combined logic and circuit designs with key elements of the planned layout topology, like signal-line order, building blocks placements and approximate gate positions. This approach required to perform the logic and circuit design concurrently to produce a document where the placement of the transistors reflected as much as possible their expected position in the layout. This way, the time required to perform the logic design, circuit design and the layout was minimized, and possible translation errors avoided. Faggin also devised a number of standardized circuit blocks together with simple rules to rapidly calculate the transistor dimensions based on load factors that could be determined with reasonable precision from the design document itself, since such document mirrored as closely as possible the layout plan of the chip.
The layout started with a grid of poly-silicon and aluminum lines carrying the key signals. The circuits were “tucked” underneath the grid, reflecting as much as possible the spatial location in the blueprint. Combining the SGT with these techniques, a factor-of-two improvement in circuit density, and a factor-of-five to ten improvement in speed-power product were achieved over equivalent metal-gate designs. Without the SGT and without SGDM, a useful microprocessor could not have been designed in 1970.
After the successful design of the 4004, its layout and the methodology used in its design provided an important source of techniques and implementation examples that were used at Intel and other companies for the design of complex random logic chips. Faggin’s SGDM was also applied to all early microprocessors at Intel and at Zilog (8008, 8080, 4040, Z80 and Z8).
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