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Faggin’s Bootstrap Load and Buried Contact Rescue Hoff’s Architecture
By the mid-Sixties it was well known how to architect and design small CPUs that could be implemented in several chips. But to achieve the required speed and cost target for many practical applications, it was necessary to fit the CPU into a single chip. The problem was the lack of a viable technology to do so with the proper speed, power dissipation, and manufacturing cost.
In 1968, the MOS silicon gate technology, developed by Federico Faggin at Fairchild Semiconductor, allowed to achieve 5 times the speed of the incumbent MOS metal gate technology and could pack twice as many random logic transistors by using another invention by Faggin: the buried contact. However, there was an important feature missing from the SGT: the ability to make bootstrap loads. Without them the 2-phase dynamic logic contemplated in Hoff’s architecture could not be used. The only alternative was to use static logic which required two to three times more transistors, and had lower speed. The resolution of such impasse had to wait until early 1970, when Faggin still at Fairchild, applied his device physics knowledge to figure out how to build bootstrap-load devices. When he joined Intel in April, 1970, he utilized his buried contact and his bootstrap load for the first time in the design of the 4004. Without these vital pieces of the technological puzzle, Hoff's architecture could not have been implemented in 1970. See also Gilbert
Hyatt patent.
Faggin’s bootstrap load and buried contact proved fundamental in the methodology that he created for designing the 4004 and all the other early Intel microprocessors: 8008, 4040, and 8080, developed under his direction. Without them, the microprocessor would have been too slow and too costly for any practical application, given that the much higher speed of the SGT with bootstrap load was barely sufficient to open up the market to such a revolutionary new way of designing electronic systems.
A major drawback to the performance of the 4004 was the specific time-multiplexed bus organization that substantially reduced the throughput of the system that otherwise would have been possible with the silicon gate technology. It was dictated by the exclusive use of 16-pin packages for all the chips. By using separate lines for address and data, instead of a time multiplexed 4-bit bus, it would have been possible to create a 4004 with an instruction cycle time of 4 microseconds (3 clock cycles) instead of 10.7 microseconds (8 clock cycles). It is only because of the superiority of the silicon gate technology over metal gate that the MCS-4 performance was still better than the performance of the Rockwell PPS-4, a competing 4-bit chip set introduced in 1972, made with metal gate MOS technology and housed in a 42-pin package. The external bus organization is the subject of the patented memory addressing scheme of the Intel MCS-4 chip set: Patent No. 3,821,715.
Before the microprocessor, the only way for a system designer to reduce the number of components and lower the cost of his product, was to design one or more specialized custom MOS chips. This method, however, required very high development cost and a long development cycle, and was cost-effective only for products with very high production volume. With microprocessors, system designers could immediately use standard hardware products and fashion specialized software, rather than specialized hardware, dramatically reducing the cost and time to market for their products. This is the essence of the revolution made possible by the invention of the microprocessor, whose consequence was a massive proliferation of novel electronic products in all fields.
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